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Intel’s Integrated Graphics Mini-Review: Is Rocket Lake Core 11th Gen Competitive?
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In the last few months we have tested the latest x86 integrated graphics options on the desktop from AMD, with some surprising results about how performant a platform with integrated graphics can be. In this review, we’re doing a similar test but with Intel’s latest Rocket Lake Core 11th Gen processors. These processors feature Intel’s Xe-LP graphics, which were touted as ‘next-generation’ when they launched with Intel’s mobile-focused Tiger Lake platform. However, the version implemented on Rocket Lake has fewer graphics units, slower memory, but a nice healthy power budget to maximize. Lo, Intel set forth for battle.

When a CPU meets GPU

Intel initially started integrating graphics onto its systems in 1999, by pairing the chipset with some form of video output. In 2010, the company moved from chipset graphics to on-board processor graphics, enabling the graphics hardware to take advantage of a much faster bandwidth to main memory as well as a much lower latency. Intel’s consumer processors now feature integrated graphics as the default configuration, with Intel at times dedicating more of the processor design to graphics than to actual cores.

Intel CPUs: IGP as a % of Die Area
AnandTech Example Launched Cores IGP Size IGP as Die Area %

Sandy Bridge i7-2600K Jan 2011 4 Gen6 GT2 11%
Ivy Bridge i7-3770K April 2012 4 Gen7 GT2 29%
Haswell i7-4770K June 2013 4 Gen7.5 GT2 29%
Broadwell i7-5775C June 2015 4 Gen8 GT3e 48%
Skylake i7-6700K Aug 2015 4 Gen9 GT2 36%
Kaby Lake i7-7700K Jan 2017 4 Gen9 GT2 36%
Coffee Lake i7-8700K Sept 2017 6 Gen9 GT2 30%
Coffee Lake i9-9900K Oct 2018 8 Gen9 GT2 26%
Comet Lake i9-10900K April 2020 10 Gen9 24 EUs 22%
Rocket Lake i9-11900K March 2021 8 Xe-LP 32 EUs 21%

Mobile CPUs

Ice Lake-U i7-1065G7 Aug 2019 4 Gen11 64 EUs 36%
Tiger Lake-U i7-1185G7 Sept 2020 4 Xe-LP 96 EUs 32%

All the way from Intel’s first integrated graphics to its 2020 product line, Intel was reliant on its ‘Gen’ design. We saw a number of iterations over the years, with updates to the function and processing ratios, with Gen11 featuring heavily in Intel’s first production 10nm processor, Ice Lake.The latest graphics design however is different. No longer called ‘Gen’, Intel upcycled its design with additional compute, more features, and an extended effort for the design to scale from mobile compute all the way up to supercomputers. This new graphics family, known as Xe, is now the foundation of Intel’s graphics portfolio.

It comes in four main flavors:
  • Xe-HPC for High Performance Computing in Supercomputers
  • Xe-HP for High Performance and Optimized FP64
  • Xe-HPG for High Performance Gaming with Ray Tracing
  • Xe-LP for Low Power for Integrated and Entry Level
Intel has initially rolled out its LP designs into the market place, first with its Tiger Lake mobile processors, then with its X[sup]e[/sup] MAX entry level notebook graphics card, and now with Rocket Lake.

Xe-LP, A Quick Refresher

Intel’s LP improves on the previous Gen11 graphics by reorganizing the base structure of the design. Rather than 7 logic units per execution unit, we now have 8, and LP’s front-end can dispatch up two triangles per clock rather than one. The default design of LP involves 96 execution units, split into a centralized ‘slice’ that has all the geometry features and fixed function hardware, and up to 6 ‘sub-slices’ each with 16 logic units and 64 KiB of L1 cache. Each variant of LP can then have up to 96 execution units in a 6x16 configuration.

Execution units now work in pairs, rather than on their own, with a thread scheduler shared between each pair. Even with this change, each individual execution unit has moved to an 8+2 wide design, with the first 8 working on FP/INT and the final two on complex math. Previously we saw something more akin to a 4+4 design, so Intel has rebalanced the math engine while also making in larger per unit. This new 8+2 design actually decreases the potential of some arithmetic directly blocking the FP pipes, improving throughput particularly in graphics and compute workloads.

The full Tiger Lake LP solution has all 96 execution units, with six sub-slices each of 16 execution units (6x16), Rocket Lake is neutered by comparison. Rocket Lake has 4 sub-slices, which would suggest a 64 execution unit design, but actually half of those EUs are disabled per sub-slice, and the final result is a 32 EU implementation (4x8). The two lowest Rocket Lake processors have only a 3x8 design. By having only half of each sub-slide active, this should in theory give more cache per thread during operation, and provides less cache pressure. Intel has enabled this flexibility presumably to provide a lift in edge-case graphics workloads for the parts that have fractional sub-slices enabled.
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