Intel's Tiger Lake Growls: 10nm Chip Packs 50 Percent More L3 Cache and AVX-512

[harlan4096]

Tiger Lake-U will feature a 50% increase in L3 cache capacity, going from 8MB to 12MB, per a posting of a processor dump by @InstLatX64 on Twitter. This means a bump up to 3MB of L3 cache per core.

As expected, the Tiger Lake-U model is a quadcore with hyperthreading. The posted image also reveals that the engineering sample ran at 3.4GHz, a respectable frequency for a pre-production model.

The image also contains a heap of flags representing the supported instruction sets. It confirms AVX-512 support like Sunny Cove, but it does not seem to have the avx512_bf flag that would be expected if it had supported bfloat16 like early next year’s Cooper Lake Xeon processors.

Most notably, however, the dump shows that the quad-core Tiger Lake-U has 12MB of total L3 cache, an increase of 50% that equates to a 3MB slice of L3 per core. This fits with the cache redesign that Intel had disclosed for Willow Cove, the CPU core of Tiger Lake, although the cache redesign likely implies bigger changes than just an increase in size. For example, a larger cache has a higher latency, so there will likely be some fine-grained tuning under the hood.

Tiger Lake is set to launch next year, as we detailed previously. A benchmark has also leaked out of Tiger Lake and it will also feature the Gen 12 Xe graphics, which will have a new display feature and a big instruction set update.

Source