AMD EPYC 9006 “Venice” to feature up to 96 Zen6 or 256 Zen6c cores, 128MB L3 cache pe

[harlan4096]

12 core Zen6 CCD confirmed for EPYC Venice

6th Generation EPYC series, first to leak with Zen6 cores. 



Does anyone still remember Broly, aka Kitty Corgi? This leaker isn’t gone; he just went underground and is now sharing details on lesser-known globally platforms. Under the new name “Sepeuwmjh,” the leaker is sharing slides from an AMD presentation on EPYC “Venice,” the next-gen server CPU.

The leak confirms that Venice will adopt up to 8 CCD (Core Complex Die) configuration featuring either Zen6 or Zen6c (dense) core designs. Importantly, each CCD would feature up to 12x Zen6 cores. This means that the next EPYC configuration would feature either 96 Zen6 or 256 Zen6c cores. Furthermore, it also confirms that each CCD will have 128MB of L3 cache, enabling a total of 1GB of L3 cache.

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